1. Field of the Invention
The present invention relates to a phase detector circuit for used in a phase locked loop (PLL).
2. Description of the Related Art:
FIG. 4 is block diagram showing a structure of a general PLL.
A PLL comprises a phase detector 1, a charge pump 2, a low pass filter 3, a voltage-controlled oscillator 4, and a frequency divider 5. The phase detector 1 compares phases of a reference clock BCK and of a divided clock obtained by dividing an oscillation clock OCK (described later) of the voltage-controlled oscillator 4 to generate outputs PDU, PDD according to the phase difference. The charge pump 2 has a positive constant-current source for supplying a constant current to the output side, and a negative constant-current source for drawing a constant current from the output side, and charges/discharges the low pass filter 3 according to outputs PDU, PDD. The low pass filter 3 removes AC components from the output PD supplied by the charge pump 2, and outputs a voltage Vc which varies according to the output PD. The voltage-controlled oscillator 4 alters an oscillation operation in response to the voltage Vc applied thereinto via the low pass filter 3 to generate an oscillation clock OCK having a frequency according to the voltage Vc. The frequency divider 5 divides an oscillation clock OCK input from the voltage-controlled oscillator 4 at a predetermined ratio to supply a divided clock TCK to the phase detector 1. In the frequency divider 5, an oscillation clock may be divided, for example, into half so that a divided clock TCK with a duty ratio of 1/2 can be obtained.
With the above PLL, the oscillation frequency of the voltage-controlled oscillator 4 is controlled according to the phase difference between a reference clock BCK and an oscillation clock OCK so that a constant phase difference can be maintained between a reference clock BCK and an oscillation clock OCK.
FIG. 5 is a circuitry diagram showing a structure of a phase detector 1. FIG. 6 is a timing chart explaining the operation of the phase detector 1.
The phase detector 1 includes three flip flops 11, 12, 13 and two XOR (exclusive OR) gates 14, 15. The three flip flops 11, 12, 13, are serially connected, and together constitute a shift register. The flip flop 11 at the first stage receives, via its D-input, a reference clock BCK. The flip flops 11, 12 at the first and second stages, respectively, receive, via each T-input thereof, a divided clock TCK. The flip flop 13 at the third stage receives, via T-input thereof, an inverted clock of a divide clock TCK. With this arrangement, the state of a reference clock BCK is transferred to the flip flops 11, 12 at the first and second stages, respectively, in response to the rise (leading edge) of a divided clock TCK, and further to the flip flop 13 at the third stage in response to the fall (trailing edge) of the divided clock TCK.
The first XOR gate 14 is connected, via two inputs thereof, to the input of a reference clock BCK and to the Q-output of the flip flop 11, respectively, and supplies a logical (exclusive OR) output of the received signals as a comparison output PDU to the charge pump 2. The second XOR gate 15 is connected, via two inputs thereof, to Q-output of the flip flop 12 and Q-output of the flip flop 13, supplies a logical (exclusive OR) output of the received signals as a comparison output PDD to the charge pump 2.
The operation of the above described phase detector 1 will next be described referring to FIG. 6.
A reference clock BCK is taken into the flip flop 11 at the rise of a divided clock TCK. Then, an output Q1 from the flip flop 11 changes following the reference clock BCK, at the rise of the divided clock TCK after the change of the reference clock BCK. Receiving a reference clock BCK and an output Q1, the XOR gate 14 continues sending an output PDU at a low level during a period from the fall of the reference clock BCK to the following rise of the divided clock TCK, and a period from the rise of the reference clock BCK to the following rise of the divided clock TCK, whereby the positive constant-current source of the charge pump 2 is switched on.
An output Q1 from the flip flop 11 is taken into the flip flop 12 at the rise of a divided clock TCK, so that the output Q2 of the flip flop 12 forms a waveform identical to that of the output Q1 delayed by one divided clock TCK cycle. The output Q2 of the flip flop 12 enters the flip flop 13 at the fall of the divided clock TCK, so that the output Q3 from the flip flop 13 forms a waveform identical to that of the output Q2 delayed by 1/2 cycle of a divided clock TCK. Having received the outputs Q2 and Q3, the XOR gate 15 keeps sending an output PDD at a high level during a period from the rise of the output Q2 to the following rise of the output Q3, and a period from the fall of the output Q2 and the fall of the output Q3, whereby the negative constant-current source of the charge pump 2 is turned on.
Here, the comparison output PDU remains at a low level during a period corresponding to the addition of the difference between when the reference clock BCK changes (a BCK changing point) and when the divided clock TCK falls (a TCK falling point) and a half cycle of the divided clock TCK, or a period corresponding to the subtraction of the former from the latter. That is, in the case where a divided clock TCK lags with respect to a reference clock BCK, the comparison output PDU remains at a low level during a period corresponding to the difference between the BCK changing point and the TCK falling point during a period from the BCK changing point to the TCK falling point and the following half cycle of the divided clock TCK. In the opposite case, i.e., where the divided clock TCK leads, the comparison output PDU remains at a low level during a period shorter than a half cycle of the divided clock TCK by a period corresponding to the difference between the BCK changing point and the TCK falling point.
On the other hand, comparison output PDD becomes a high level at a timing delayed by one divided clock TCK cycle from the rise of the comparison output PDU (a PDU rising point), and thus remains in a half cycle of the divided clock TCK. The comparison output PDD cancels, in the charge pump 2, the "addition" period included in the period with the comparison output PDU at a low level (corresponding to a half cycle of the divided clock TCK), whereby the period with a low-level output PDU is controlled to be shortened depending on the phase difference between the reference clock BCK and the divided clock TCK.
In the above phase detector 1, a period corresponding to a period when the divided clock TCK for operating the flip flops 11-13 remains at a low level is included in the period when the comparison output PDU remains at a low level, and a period with a comparison output PDD at a high level is determined according to the period with the divided clock TCK at a high level. Therefore, the divided clock TCK must be set such that high and low level period become equal. In other words, the duty ratio of a divided clock TCK must be set at 1/2. In a voltage-controlled oscillator, in which the duty ratio of an oscillation clock is unstable, an oscillation clock is divided to obtain a clock with a 1/2 duty ratio. This causes a problem such that the oscillation frequency of the voltage-controlled oscillator 4 must be set twice or more as large as the frequency of a divided clock TCK which is used in comparison in the phase detector 1.